1. Field of the Invention
The present invention is directed in general to the field of semiconductor devices. In one aspect, the present invention relates to high-performance complementary metal oxide semiconductor (CMOS) field effect transistors (FETs) fabricated on hybrid or dual substrates.
2. Description of the Related Art
To address the difference in electron and hole mobility values for NMOS and PMOS transistor devices formed on semiconductor wafers having a single crystal orientation, CMOS devices are increasingly fabricated with hybrid substrates with different surface orientations using semiconductor-on-insulator (SOI) or bulk silicon wafer bonding to provide PMOS and NMOS devices with their own optimized crystal orientation. With hybrid devices, shallow trench isolation (STI) regions are formed to isolate the substrates, and typically include a liner oxide film that is deposited and/or grown in the etched substrate trenches and covered by a filling oxide prior to chemical mechanical planarization. In addition to curing damage caused by the substrate etch process and passivating the STI sidewalls, the liner oxide improves device reliability by ensuring proper corner rounding, and eliminates device leakage by preventing formation of divots that can lead to residual polysilicon formation. Prior approaches for fabricating hybrid devices have formed the dual NMOS and PMOS substrates before forming the STI regions using conventional liner techniques. However, when one of the substrate materials (e.g., the (110) silicon used to form the PMOS devices) has a higher oxidation rate than the other substrate material (e.g., the (100) silicon used to form the NMOS devices), the liner thickness will differ between the NMOS and PMOS devices. As a result, device reliability and STI passivation will differ between the NMOS and PMOS devices. On the other hand, if the STI regions are formed in the first substrate before the second substrate is etched and filled, the liner will be only be on one side of the STI regions (e.g., on the first substrate side) but not on the other side.
Accordingly, a need exists for a semiconductor manufacturing process which provides the process and performance advantages of forming a trench liner layer for the entire STI regions used with dual substrate devices. There is also a need for a fabrication process which avoids the process and performance limitations associated forming a trench liner after the dual substrates are formed. In addition, there is a need for improved semiconductor processes and devices to overcome the problems in the art, such as outlined above. Further limitations and disadvantages of conventional processes and technologies will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow.
It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the drawings have not necessarily been drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to other elements for purposes of promoting and improving clarity and understanding. Further, where considered appropriate, reference numerals have been repeated among the drawings to represent corresponding or analogous elements.